Browse Prior Art Database

Simplified Method to Disable On-Chip Error Correction

IP.com Disclosure Number: IPCOM000103082D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 38K

Publishing Venue

IBM

Related People

Fifield, JA: AUTHOR

Abstract

To characterize memory array chips, it is necessary to disable on-chip error correction circuits (ECCs). An improved data corrector is described which includes simple means to turn off the ECC.

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Simplified Method to Disable On-Chip Error Correction

      To characterize memory array chips, it is necessary to disable
on-chip error correction circuits (ECCs).  An improved data corrector
is described which includes simple means to turn off the ECC.

      Fig. 1 is a block diagram showing n syndrome generators
contained in block 10 connected by wires S1 through Sn to m data
corrector circuits in block 12.  An m wide data bus 14 brings data in
to block 12 and data goes out of block 12 via m wide data bus
16.

      Referring to Fig. 2, devices T1 through Tn form a NOR function
needed to decode a syndrome address.  Transistor Tp precharges node
N1 when triggered by phase P.  Signal at node N1 is buffered through
inverters 18 and 20 to create an error flag signal on line 22 at
exclusive OR (XOR) 24.  A data bit on line 26 is XORed with the
associated error flag on line 22 to permit correction.  A high signal
on ECC OFF line 28 to the gate of transistor Toff provides the
disablement feature.  This insures that all m NOR decoders discharge
their nodes N1 and hold all m error flags on lines 22 low.  This
example is given for a precharged dynamic NOR but can also be done in
static or other dynamic decode circuits.

      Disclosed anonymously.