Browse Prior Art Database

Multiple "Soft" I/O Locations to Minimize Pad Transfer Resistance

IP.com Disclosure Number: IPCOM000103084D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 33K

Publishing Venue

IBM

Related People

Gould, EL: AUTHOR

Abstract

By defining two or more legal chip locations for input/output (I/O) circuits instead of the usual chip periphery locations, chip designers can minimize I/O connection resistance when necessary. This technique is especially useful for layout of large chips having centrally located reflow solder interconnection pads.

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Multiple "Soft" I/O Locations to Minimize Pad Transfer Resistance

      By defining two or more legal chip locations for input/output
(I/O) circuits instead of the usual chip periphery locations, chip
designers can minimize I/O connection resistance when necessary.
This technique is especially useful for layout of large chips having
centrally located reflow solder interconnection pads.

      Referring to the figure, legal I/O circuit locations on chip 2
periphery are shown as rectangular areas.  Use of location 4 for an
I/O circuit having reflow solder pad location 6 would lead to the
necessity of a pad transfer conductive line 8 in the next level of
metal.  However, use of a legal alternative I/O circuit placement
area 10 enables the circuit designer to significantly shorten the
length of transfer line 8 and to thereby minimize electrical
resistance in I/O connections when necessary.

      Power bus line areas are defined to be contained in the I/O
circuit legal placement areas.  Thus, when an alternate area is
selected, the power bus structure is automatically placed along with
the I/O circuit.

      Disclosed anonymously.