Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Revised Complement/Recomplement With On-Chip Error Correction

IP.com Disclosure Number: IPCOM000103145D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 48K

Publishing Venue

IBM

Related People

Brearly, AW: AUTHOR [+3]

Abstract

System or card level error correction cannot perform complement and recomplement steps to recover from double bit errors in a card error correction word when memory chips have on-chip error correction for single bad bits internal to a chip. By complementing all data bits in an internal error correction word at a "write complement" step, on-chip error correction may be left on while providing successful complement and recomplement steps to the card or system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 80% of the total text.

Revised Complement/Recomplement With On-Chip Error Correction

      System or card level error correction cannot perform complement
and recomplement steps to recover from double bit errors in a card
error correction word when memory chips have on-chip error correction
for single bad bits internal to a chip.  By complementing all data
bits in an internal error correction word at a "write complement"
step, on-chip error correction may be left on while providing
successful complement and recomplement steps to the card or system.

      To complement all error correction word data bits at the "write
complement" step: First, column address signal (CAS) is rippled
through read - modify - write cycles over all error correction word
data bits at the card level to successively read and write-complement
the data.  Second, fetch complemented data and recomplement at the
card or system error correction level.  Third, repeat read - write -
complement at all error correction word data bits to return array
data to the proper state.  Once a failing page is identified and
removed from use, complement and recomplement occurs infrequently,
thus minimizing any performance penalty.

      A second method may be used when performance is a key issue.  A
new initial program load (IPL) code is defined to have memory chip
logic perform "read complement" and "write complement" in the
complement and recomplement steps on all error correction data bits.
This operation is triggered by c...