Browse Prior Art Database

Integrated Vertical Packaging Technique

IP.com Disclosure Number: IPCOM000103156D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 35K

Publishing Venue

IBM

Related People

Carden, G: AUTHOR [+5]

Abstract

Disclosed is a procedure to maximize function by stacking components and shortening interconnections between components.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Integrated Vertical Packaging Technique

      Disclosed is a procedure to maximize function by stacking
components and shortening interconnections between components.

      Prior assembly methods package support devices, such as
amplifier chips, in separate substrates, cards, etc.  This will
generally result in longer interconnections, larger packages and even
cross-overs.

      To improve the problems associated with such other packaging
techniques, copper plated polyimide is adhesively laminated to the
surface of a back-bonded preamplifier chip or support device.  As
shown in Fig. 1, a pin diode chip is back bonded to the copper clad
polyimide directly above the amplifier chip.  In a device package
configuration such as this, wire bond lengths are reduced to the
package's pins, preamp pads and photo diode pads.  This can again be
enhanced by introducing a thermal stabilization plate, as shown in
Fig. 2, where a 2-oz. copper lead frame is used to isolate heat
generated by the back-bonded preamp chip from the photo detector.

      Disclosed anonymously.