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The Use of Low Temperature, Low Pressure Intrinsic Silicon Epi to Seal P+ Wafers

IP.com Disclosure Number: IPCOM000103162D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 49K

Publishing Venue

IBM

Related People

Bendernagel, RE: AUTHOR [+2]

Abstract

The vapor pressure of boron in silicon is such that, at elevated temperatures, the evaporation of boron into the vapor phase can be quite high. In the deposition of lightly doped epi on silicon wafers doped heavily with boron, wafers are subjected to temperatures greater than 1000oC. High temperatures are used in order to maintain throughput. As a result, boron autodoping occurs which leads to poor uniformity control of the dopant within the deposited epi.

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The Use of Low Temperature, Low Pressure Intrinsic Silicon Epi to Seal P+ Wafers

      The vapor pressure of boron in silicon is such that, at
elevated temperatures, the evaporation of boron into the vapor phase
can be quite high.  In the deposition of lightly doped epi on silicon
wafers doped heavily with boron, wafers are subjected to temperatures
greater than 1000oC.  High temperatures are used in order to maintain
throughput.  As a result, boron autodoping occurs which leads to poor
uniformity control of the dopant within the deposited epi.

      To prevent autodoping, p+ wafers are sealed with a film which
inhibits boron evaporation.  Presently, these films include silicon
dioxide and intrinsic polysilicon.  These films cover the backside of
wafers and their effectiveness is limited.  Low temperature, low
pressure intrinsic epi can seal on both sides of the wafer.

      As a sealing process, low temperature epi produces a better
surface to deposit epi on than the conventional methods.  With
silicon dioxide sealing and polysilicon sealing, the oxide or poly
film must be polished off the front surface.  Polishing may leave
some damage and definitely attacks the denude zone created by prior
preanneal processing.

      One other problem associated with oxide sealing is that the
oxide at the edge of the wafer may contain pinholes which expose the
silicon substrate.  During the subsequent deposition of epi, a
selective epi process occurs in the pi...