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Electrical Contacts Through Planar Isolation

IP.com Disclosure Number: IPCOM000103185D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 39K

Publishing Venue

IBM

Related People

Debrosse, JK: AUTHOR [+4]

Abstract

Integration is an increasingly important step in integrated circuit fabrication and several techniques have been recently disclosed for the formation of planar, dielectric-filled, isolation trenches. In one such method, isolation trenches are etched and filled with a dielectric. A sacrificial layer is then deposited over the filled trenches and this layer is chosen to have a very rapid chemical-mechanical polish (CMP) rate compared to the underlying dielectric layer. The structure is then CMP'ed, resulting in a planar structure. Planarity is then transferred to the substrate level.

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Electrical Contacts Through Planar Isolation

      Integration is an increasingly important step in integrated
circuit fabrication and several techniques have been recently
disclosed for the formation of planar, dielectric-filled, isolation
trenches.  In one such method, isolation trenches are etched and
filled with a dielectric. A sacrificial layer is then deposited over
the filled trenches and this layer is chosen to have a very rapid
chemical-mechanical polish (CMP) rate compared to the underlying
dielectric layer.  The structure is then CMP'ed, resulting in a
planar structure.  Planarity is then transferred to the substrate
level.

      These methods can be utilized to form electrical contacts
through planar isolation.  First, isolation trenches are etched and
filled.  Contacts are then defined photolithographically and the
trench fill material is removed from these areas.  (Fig. 1.)  An
electrically conductive sacrificial layer is then deposited and the
structure is planarized by CMP.  Planarity is then transferred to the
substrate level resulting in the structure shown in Fig. 2.  These
contacts can be used to form the collector contact in a vertical
bipolar transistor or well and substrate contacts in MOS
applications.

      Disclosed anonymously.