Browse Prior Art Database

Computer Hardware Testcase Supervisor

IP.com Disclosure Number: IPCOM000103200D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 38K

Publishing Venue

IBM

Related People

Hoffman, H: AUTHOR [+2]

Abstract

Disclosed is a method for verifying the functionality of computer hardware using AVPs (hardware Architectural Verification Programs).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Computer Hardware Testcase Supervisor

      Disclosed is a method for verifying the functionality of
computer hardware using AVPs (hardware Architectural Verification
Programs).

      The supervisor loads the AVP directly into the memory of the
machine, runs the AVP and logs errors.  The supervisor consists of
code which is loaded into reserved memory (along with all AVPs to be
run) and will take each set of AVP instructions and data and moves
them from the reserved memory area to the actual memory locations
required for testcase execution.  As the AVP runs, all errors that
are encountered are stored in another place in reserved memory.
These can be observed later using a support processor screen that
projects memory from this area.  After a testcase has been run and
errors are logged, the next testcase can be moved into its run area.
This process continues until there are no more testcases left to run.
At this time, the supervisor does some cleanup and stops the run on
the machine.

      One benefit of this technique is that other than the initial
load of contiguous memory to place the supervisor and the testcases
in memory, all other initialization, checking of results and logging
of errors is done by software running in the machine under test at
hardware speeds.  Another advantage is that this technique makes use
of many tools that already exist for the simulation models.

      Disclosed anonymously.