Browse Prior Art Database

Means for Improving Testcase Execution in a Hardware Simulator And Real Hardware Testing

IP.com Disclosure Number: IPCOM000103202D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 58K

Publishing Venue

IBM

Related People

Hoffman, H: AUTHOR [+4]

Abstract

Disclosed is a means of efficiently executing testcases on both a hardware-based simulator and on real hardware by compressing and buffering the testcases.

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Means for Improving Testcase Execution in a Hardware Simulator And Real Hardware Testing

      Disclosed is a means of efficiently executing testcases on both
a hardware-based simulator and on real hardware by compressing and
buffering the testcases.

      A hardware-based simulator is able to simulate logic at very
fast speeds due to special purpose hardware used to simulate logic
gates and memory.  However, its performance may be reduced
dramatically if the simulation methodology requires a lot of accesses
from the host control computer. One type of access that is generally
required is to load the testcase instructions into memory.
Simulators based on software algorithms generally do not suffer from
such a problem, as they are much slower than simulators with hardware
accelerators, and the physical grouping of accessed data is typically
much more convenient than in a hardware-based simulator.  Therefore,
the problem is to take a testcase methodology that functions well
with a software-based simulator, and make it work well on a
hardware-based simulator.

      The same problem occurs for real hardware testing, as accesses
via an external control computer are often millions of times slower
than accesses by the hardware under test.

      Instead of having the host control computer directly load a
single set of testcase instructions, the testcase instructions are
first formatted and compressed.  Then multiple sets of these
formatted instructions represen...