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Buried Trench, Contact in a Contact DRAM Cell Structure

IP.com Disclosure Number: IPCOM000103207D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 44K

Publishing Venue

IBM

Related People

Bertsch, JE: AUTHOR [+2]

Abstract

A one device dynamic random access memory (DRAM) cell is comprised of a buried storage trench and a vertical transistor structure. Complementary metal oxide silicon technology is used in making this cell structure which occupies very small silicon surface area.

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Buried Trench, Contact in a Contact DRAM Cell Structure

      A one device dynamic random access memory (DRAM) cell is
comprised of a buried storage trench and a vertical transistor
structure.  Complementary metal oxide silicon technology is used in
making this cell structure which occupies very small silicon surface
area.

      Referring to the figure, a trench is etched in heavily doped P+
substrate 2.  Trench walls are coated with dielectric 4 before P+
polysilicon 6 is deposited and planarized to fill the trench.  N-type
silicon 8 is epitaxially deposited, which is also used for N-wells
under planar devices in peripheral circuits.  Following planar device
processing, reflowable insulator 10 is deposited.  A hole is opened
through insulator 10 to epitaxial silicon 8 and P+ polysilicon 12 bit
line material is deposited.  Using a self- aligned masking method, a
central hole is anisotropically etched to trench polysilicon 6.  High
quality gate dielectric 14 is deposited and P+ polysilicon gate
electrode and word line 16 is deposited.  Annealing is performed to
diffuse dopant impurities from polysilicon 12 and 6 to form bit line
diffusion 18 and storage node diffusion 20 in n-type epitaxial
material 8.

      Disclosed anonymously.