Browse Prior Art Database

Glitch-Insensitive Synchronizer Circuit

IP.com Disclosure Number: IPCOM000103216D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 40K

Publishing Venue

IBM

Related People

Welte, RG: AUTHOR

Abstract

Disclosed is a circuit design that will synchronize asynchronous signals to a clocked system. It has the feature of being insen sitive to glitches on the asynchronous signal.

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This is the abbreviated version, containing approximately 100% of the total text.

Glitch-Insensitive Synchronizer Circuit

      Disclosed is a circuit design that will synchronize
asynchronous signals to a clocked system.  It has the feature of
being insen sitive to glitches on the asynchronous signal.

      A double latch implementation is used for synchronization and
to eliminate metastable conditions.  Two "D" latches are clocked with
the system clock.  The first latch is set when the asynchronous
signal is present and the clock is activated.  The second latch is
set on the next clock cycle only if the synchronous signal is still
present. If the asynchronous signal is no longer present, then the
first latch is reset, and the second latch remains in a reset state.

      Once both latches are set, if the asynchronous signal is not
present when the clock is activated, the first latch will be reset.
The second latch is reset one clock cycle after the first latch is
reset only if the asynchronous signal remains inactive.  In this
manner, a glitch which is less than a clock period long (negative or
positive) will not be propagated to the output of the second latch.

      The output of the second latch is synchronized to the system
clock, insensitive to glitches on the asynchronous input signal, and
free from the effects of a possible metastable state in the first
latch.

      Disclosed anonymously.