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Improved Solder Joint Life Using Dendritic TSM Metallization

IP.com Disclosure Number: IPCOM000103238D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 68K

Publishing Venue

IBM

Related People

Kim, J: AUTHOR [+4]

Abstract

The mismatch of thermal expansion between Si chips and ceramic module (or epoxy board) substrates results in a thermal stress in Si devices causing a thermal fatigue failure of the solder joints. Disclosed are a new morphology and fabrication process of top surface metallurgy (TSM) of ceramic module (or epoxy board) substrates to minimize thermal fatigue failure of chip solder joints and to increase fatigue life of solder joints.

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Improved Solder Joint Life Using Dendritic TSM Metallization

      The mismatch of thermal expansion between Si chips and ceramic
module (or epoxy board) substrates results in a thermal stress in Si
devices causing a thermal fatigue failure of the solder joints.
Disclosed are a new morphology and fabrication process of top surface
metallurgy (TSM) of ceramic module (or epoxy board) substrates to
minimize thermal fatigue failure of chip solder joints and to
increase fatigue life of solder joints.

      Fatigue life of solder joints can be increased by providing a
continuous but rough and irregular interface between solder and TSM.
This minimizes the crack propagation path length and, therefore,
stops crack propagation.  One way to provide such an optimized
interface is to electroplate the TSM utilizing high current density
to produce a classic dendritic morphology.  For example, Pd dendrites
of 1 - 2 mils in height can be grown onto the TSM using high
current density (100mA/cm*2).  Overplating the dendritic Pd with Au
may improve the solderability.  Si chips with solder bumps can then
be joined following standard joining processes and the resulting
interface is shown in Figure.

      Disclosed anonymously.