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High Voltage Reliability Screen Using Stepped Pattern/Power Supply for CMOS Circuits

IP.com Disclosure Number: IPCOM000103262D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 41K

Publishing Venue

IBM

Related People

Lyon, DL: AUTHOR

Abstract

By lowering the power supply voltage for chip level voltage screening CMOS circuits before applying a test pattern and then applying the full operating voltage that the circuits can handle statically, potential device damage can be eliminated during burn-in.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 94% of the total text.

High Voltage Reliability Screen Using Stepped Pattern/Power Supply for CMOS Circuits

      By lowering the power supply voltage for chip level voltage
screening CMOS circuits before applying a test pattern and then
applying the full operating voltage that the circuits can handle
statically, potential device damage can be eliminated during burn-in.

      CMOS circuits may be damaged by switching at high voltages on
the power supplies during burn-in due to high substrate currents
flowing in the structure. The source of these currents is believed to
be due to impact ionization in the source/drain/ drain region during
switching of the circuit. Static safe voltage is often 3 or 4 volts
higher than a safe switching voltage.

      The procedure is to power up chips to be voltage screened and
apply normal setup for testing. Apply the first test (screen)
pattern. While  holding the pattern, step Vdd up to the static screen
voltage condition for some period of time. Next, step the screen
voltage back to a safe level for circuit switching. When changing the
input test pattern, wait for the chips to stabilize before stepping
Vdd back up to the static screen condition for hold time. Repeat this
procedure for all of the read screen patterns.

      Following the procedure disclosed will result in stressing
internal lines on the chips to a maximum while protecting good chips
by switching the circuits at a safe value. Reliability screening
effectiveness is maximized and...