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Method for optimizing transition fault test effectiveness of various logic paths with various physical properties.

IP.com Disclosure Number: IPCOM000103276D
Original Publication Date: 2005-Mar-17
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 25K

Publishing Venue

IBM

Abstract

Transition fault-based delay test traditionally assumes that all transition faults are equally important. This publication describes a method by which transition faults can be ordered according to those that represent defects most likely to occur. Test pattern generation will then target the transition faults in the order determined, first generating for faults mostly likely to detect real defects. The transition faults will be prioritized based on vias between certain levels of metal, on the number of vias on a net, on the length of a net, or on any other such physical characteristic. The likelihood of such defects will vary over time in a manufacturing facility and this method allows the ordering to be varied to reflect the current manufacturing defects.

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Method for optimizing transition fault test effectiveness of various logic paths with various physical properties.

Today's deep-submicron designs must use some kind of delay test method to detect delay faults in logic circuits. Test generation against transition faults has proven to be a very good method and is widely used. Multiple methods exist for generating patterns to perform such tests. None of today's methods take into account the relative likelihood of a transition fault on a particular net due to it's physical layout properties.

The main source of transition delay faults in copper-based technologies is contact and via resistive opens. If physical is combined with the fault model such that delay faults are given weights based upon physical information such as the number of vias in the net associated with the fault, this can be used to generate a more effective test pattern set.

Today, for example, two nets of identical logic topology, may be vastly different with respect to the number of vias and contacts that must be traversed for a signal to travel from one end of the net to the other. If the first net has two vias and the second net has 20 vias, then it is roughly 10 times more likely that the second net will contain a resistive via (a manifestation of a transition fault) than the first net.

Knowing this information, the test pattern generator would focus on the nets with more vias (or other features) and thus more chance of having manufacturing defects.

The prioritization for transition fault test pattern generation could be based on via and contact count, types of vias (redundant vs. simplex, dimensions), and what wiring levels the vias are between. A knowledge of manufacturing line defect probabilities would be used to assign weights for different types of vias or other potential delay defects.

Transition faults are slow-to-rise and slow-to-fall faults on the inputs and outputs of logic gates. The input transition faults would get higher priority based on the net they are connected to, traced back to its source. Each priority feature found on the net would increase this fault's weight. A simple example is shown in Figure 1, based solely on the via count.

1

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5 vias

10 vias

20 vias

A

B

C

D

Fig 1 Consider the net above, with source A and sinks B, C and
D. One simple embodiment would be to identify the number of vias from source A to each sink B, C and D and prioritize the sink pins with higher via counts. In this example, the input into gate D is given top priority due to the number of vias used in the path back to the source.

The priority weighting can...