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Browse Prior Art Database

Byte Serializer/Deserializer Multi-Function Unit

IP.com Disclosure Number: IPCOM000103281D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Clemen, R: AUTHOR [+3]

Abstract

In microcomputer systems, the processor unit (PU) communicates with attachments via buses. Such attachments often run asynchronously to the PU, apart from the fact that they handle data in a format different from that of the PU. To suit those applications, special interfaces are required for synchronizing the data communications and for adapting data formats. For this purpose, parallel-to-serial and serial-to- parallel conversions have to be carried out and the data has to be buffered in registers.

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Byte Serializer/Deserializer Multi-Function Unit

       In microcomputer systems, the processor unit (PU)
communicates with attachments via buses.  Such attachments often run
asynchronously to the PU, apart from the fact that they handle data
in a format different from that of the PU. To suit those
applications, special interfaces are required for synchronizing the
data communications and for adapting data formats.  For this purpose,
parallel-to-serial and serial-to- parallel conversions have to be
carried out and the data has to be buffered in registers.

      An area- and performance-effective matrix is proposed which
comprises fully static memory cells with multi-purpose functions and
which combines data conversion and synchronization in one unit.

      Fig. 1, for example, shows a matrix of 8 x 9 cells with 72
parallel inputs and 72 parallel outputs.  This matrix can be loaded
and unloaded via a serial byte interface.

      The CMOS embodiment is shown in Fig. 2.  In this embodiment a
fully static cell with a single-ended read/write port is implemented.
The inputs as well as the outputs are controlled by transmission gate
multiplexers.