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Ni/Cr/Cu Masking for Etching Circuitized Polymer Films

IP.com Disclosure Number: IPCOM000103284D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 63K

Publishing Venue

IBM

Related People

Clementi, RJ: AUTHOR [+6]

Abstract

The placement of Ni or Cr layers over Cu seed and circuitry metals during the fabrication of thin film semiconductor chip packages prior to dielectric etch patterning has been found to: 1) Allow for replacement of non-aqueous photoresist systems with aqueous photoresist systems and in turn eliminate the use of associated halocarbon (CFC) stripper and developer solutions; 2) Form in-situ pinhole-free patterned masking layers capable of acting as metallic etch masks for polymer etch definition; and 3) Provide a means of fabrication whereby the profiles of Cu circuit lines may be preserved during metal mask removal.

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Ni/Cr/Cu Masking for Etching Circuitized Polymer Films

      The placement of Ni or Cr layers over Cu seed and circuitry
metals during the fabrication of thin film semiconductor chip
packages prior to dielectric etch patterning has been found to:
      1)   Allow for replacement of non-aqueous photoresist systems
with aqueous photoresist systems and in turn eliminate the use of
associated halocarbon (CFC) stripper and developer solutions;
      2)   Form in-situ pinhole-free patterned masking layers capable
of acting as metallic etch masks for polymer etch definition; and
      3)   Provide a means of fabrication whereby the profiles of Cu
circuit lines may be preserved during metal mask removal.

      On many Thin-Film products the signal and/or ground plane
circuitry are formed by pattern plating Cu from a thin plating Cu
from a thin seed (strike) layer which has been deposited by other
means.  Significant benefits can be realized if this thin Cu seed
layer can be patterned to serve as an etch mask for the underlying
dielectric material.  However, this seed layer is typically thin and
discontinuous precluding its use.  While thicker, pinhole-free Cu
seed layer deposits allow successful dielectric etch patterning, Cu
circuit line profiles are degraded significantly during subsequent
seed layer etch processes.  Therefore, Ni and Cr layers have been
deposited by both electrolytic (Ni and Cr) and electroless (Ni only)
means upon the seed laye...