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Bicmos Comparator Circuit

IP.com Disclosure Number: IPCOM000103288D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 33K

Publishing Venue

IBM

Related People

Dawson, JW: AUTHOR

Abstract

Disclosed is a circuit that compares two input signals, A and B. The use of FET's F5 and F6 allow for a lower reference voltage VR, and therefore lower A input levels, without saturation concerns. When input A is low, T2 and T3 set the voltage levels at nodes N1 and N2 respectively. Devices T5 and T6 do not have a saturation concern since they are FET's.

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Bicmos Comparator Circuit

      Disclosed is a circuit that compares two input signals, A and
B.  The use of FET's F5 and F6 allow for a lower reference voltage
VR, and therefore lower A input levels, without saturation concerns.
When input A is low, T2 and T3 set the voltage levels at nodes N1
and N2 respectively. Devices T5 and T6 do not have a saturation
concern since they are FET's.

      When inputs A and B match, output TRUE is high.  When inputs A
and B do not match, output TRUE is low.  Output COMP is the opposite
phase of TRUE.

      Current will flow through either R1 or R2, depending on which
devices are on, resulting in TRUE and COMP outputs. When A and B are
both high, the current path will be through R1, T1 and T5.  When A
and B are both low, the path is through R1, T3 and T6.  This results
in output COMP being low when the inputs match.

      When the inputs do not match, current flows through R2 and then
through T4 and T6 or through T2 and T5.  This results in output TRUE
being low.

      R3, T7 and T8 form the current source.

      Disclosed anonymously.