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A Method to Detect Defects in Redundant Wire Interconnects On CMOS Or BiCMOS Chips

IP.com Disclosure Number: IPCOM000103289D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 33K

Publishing Venue

IBM

Related People

Plass, DW: AUTHOR [+2]

Abstract

Disclosed is a technique to detect defects in BiCMOS or CMOS redundant interconnects. As shown in the figure, redundant interconnects occur when two different conductors (e.g., metal and polysilicon) are shunted together by vias forming a ladder network. If the metal breaks, current flows through the metal before the break, then through the polysilicon, and finally through the metal to the capacitive load. The break adds a finite resistance to the transmission line and thus causes an RC delay.

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A Method to Detect Defects in Redundant Wire Interconnects On CMOS Or BiCMOS Chips

      Disclosed is a technique to detect defects in BiCMOS or CMOS
redundant interconnects.  As shown in the figure, redundant
interconnects occur when two different conductors (e.g., metal and
polysilicon) are shunted together by vias forming a ladder network.
If the metal breaks, current flows through the metal before the
break, then through the polysilicon, and finally through the metal to
the capacitive load.  The break adds a finite resistance to the
transmission line and thus causes an RC delay.

      To detect the defect, a current sink (NFET) is added to the end
of the transmission line.  When active, the current sink causes a
voltage, drop across a resistive region.  The additional voltage drop
makes circuits, attached to the transmission line beyond the break,
fail functional (i.e., DC) test.

      Disclosed anonymously.