Browse Prior Art Database

Improved Error Detection Using MP Fields

IP.com Disclosure Number: IPCOM000103309D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 50K

Publishing Venue

IBM

Related People

Levenstein, SB: AUTHOR

Abstract

Many parts of a multiprocessor system can be duplicated to improve arbitration performance. It is desirable to have some sort of check that guarantees the processors are in sync with each other. However, it is not desirable to add extra pins to multiprocessor systems to detect such out-of-sync errors.

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This is the abbreviated version, containing approximately 72% of the total text.

Improved Error Detection Using MP Fields

      Many parts of a multiprocessor system can be duplicated to
improve arbitration performance.  It is desirable to have some sort
of check that guarantees the processors are in sync with each other.
However, it is not desirable to add extra pins to multiprocessor
systems to detect such out-of-sync errors.

      Many types of sequential errors can be caught due to illegal
combinations or patterns.  All drivers and receivers are covered by
parity including shared buses.  This method improves error detection
by including extra logic in the parity bit over the control buses
sent between processors.

      This method includes the Tie break bits in the control bus
parity:
      -  TieBreak Register.  TieBreak consists of one bit for every
processor.  Exactly one of the four bits is on at a time.
      -  LockTie Register.  A similar register with one bit
corresponding to each of the control buses.  It is used in semaphore
arbitration.
      -  Multi Processor Control Buses.  Buses used to send status
between processors.  Each processor drives one bus and receives the
buses driven by all other processors.  The bus has parity on it. This
method includes the two tie break bits for the pro cessor driving the
control bus in the control bus parity.  A processor also receives
control buses from other processors; those processors, likewise,
include the two tie break bits in their control bus parity. ...