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Browse Prior Art Database

Sio2/Gaas (GaInAs) MOS Structure by Plasma Process With a Thin Si Interface Layer

IP.com Disclosure Number: IPCOM000103322D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 32K

Publishing Venue

IBM

Related People

Batey, J: AUTHOR [+4]

Abstract

This invention shows how to make a SiO2/Si/GaAs structure on GaAs or GaInAs wafers with native oxides. These oxides are removed by HCl etch and H2 plasma. A thin Si layer is deposited in situ by sputtering or PECVD. Then an SiO2 film is deposited in situ in a SiH4, N2O, and He mixture at low pressure. Substrate temperature is /200oC. The SiO2 structure is annealed at 600oC. All dots are then formed and the capacitors are annealed at 400oC.

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Sio2/Gaas (GaInAs) MOS Structure by Plasma Process With a Thin Si Interface Layer

      This invention shows how to make a SiO2/Si/GaAs structure on
GaAs or GaInAs wafers with native oxides.  These oxides are removed
by HCl etch and H2 plasma.  A thin Si layer is deposited in situ by
sputtering or PECVD.  Then an SiO2 film is deposited in situ in a
SiH4, N2O, and He mixture at low pressure.  Substrate temperature is
/200oC.  The SiO2 structure is annealed at 600oC.  All dots are then
formed and the capacitors are annealed at 400oC.

      A capacitance-voltage plot is shown in Fig. 1.  A dip in the
Q-S curve is observed.  The 1 MHz plot shows that when the voltage
goes from positive to negative, the MOS device goes from accumulation
to deep depletion under dark condition.  If now the MOS is
illuminated, it goes into inversion.

      Disclosed anonymously.