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Browse Prior Art Database

Real Time Discarding of Unwanted Logic Analyzer Traces

IP.com Disclosure Number: IPCOM000103362D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 34K

Publishing Venue

IBM

Related People

Comp, CM: AUTHOR

Abstract

Described is a real time method of discarding unwanted logic analyzer traces that would have otherwise used up the logic analyzer's trace memory. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Real Time Discarding of Unwanted Logic Analyzer Traces

      Described is a real time method of discarding unwanted logic
analyzer traces that would have otherwise used up the logic
analyzer's trace memory.

                            (Image Omitted)

      For normal logic tracing sequences the logic analyzer's inputs
1 are sampled and stored in the analyzer's memory 2. After each
sample is stored the loadable address counter 4 for the analyzer's
memory is incremented.  Later when the tracing is finished the logic
analyzer's memory is displayed to show the history of the input
states.

      For the special save/discard tracing sequences, additional
procedure steps occur.  When a condition occurs that is used to
determine when the save/discard tracing should begin, latch 3 is
activated and the current value of the counter is latched.  The
tracing will continue as usual until the condition occurs where the
save/discard is to be made.  If the decision is to save the trace,
counter 4 is left alone.  If the decision is to discard the trace
information, counter 4 is loaded from latch 3.  This process occurs
in real time.

      Disclosed anonymously.