Browse Prior Art Database

Adaptive Bus Dotting

IP.com Disclosure Number: IPCOM000103386D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 45K

Publishing Venue

IBM

Related People

Waldecker, DE: AUTHOR

Abstract

The High Performance System shown has separate data busses (6,7,8) for transfer of data between the ICU (1) and the DCU (4), the FXU (2) and the DCU (4), the FPU (3) and the DCU (4). These busses may be bidirectional (7,8) or unidirectional (6). The multiple busses (6,7,8) permit overlap of data transfer between units, thus improving system performance. The multiple busses (6,7,8) require separate input/output pins on the DCU (4), which may require multiple parts (i.e., VLSI chips) in order to accommodate the high number of pins. The multiple parts in the DCU can accommodate a larger number of cache memory words which also improves performance. The Low Cost System has the same units for ICU (9), FXU (10), and FPU (11) as the High Performance System. However, the separate busses are dotted into a single common bus (13).

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Adaptive Bus Dotting

      The High Performance System shown has separate data busses
(6,7,8) for transfer of data between the ICU (1) and the DCU (4), the
FXU (2) and the DCU (4), the FPU (3) and the DCU (4).  These busses
may be bidirectional (7,8) or unidirectional (6).  The multiple
busses (6,7,8) permit overlap of data transfer between units, thus
improving system performance.  The multiple busses (6,7,8) require
separate input/output pins on the DCU (4), which may require multiple
parts (i.e., VLSI chips) in order to accommodate the high number of
pins.  The multiple parts in the DCU can accommodate a larger number
of cache memory words which also improves performance.  The Low Cost
System has the same units for ICU (9), FXU (10), and FPU (11) as the
High Performance System.  However, the separate busses are dotted
into a single common bus (13).  The Functional Unit design is
identical for the two systems. (i.e., the ICU (1) is identical to ICU
(9), FXU (2) is identical to FXU (10), FPU (3) is identical to FPU
(11).)     The DCU (12) requires fewer parts (VLSI chips) than the
DCU (4). This invention permits the use of Functional Units with the
same design in two different systems.  The system performance may be
varied by the use of separate or combined busses for data transfer as
well as by use of different cache sizes.

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      Disclosed anonymously.