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Process Flow for First-Level Interconnect Formation in Coreless Package with Mixed/Unmixed Size Flip Chip Bumps

IP.com Disclosure Number: IPCOM000103400D
Publication Date: 2005-Mar-17
Document File: 3 page(s) / 182K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that enables the creation of a coreless package with mixed and/or unmixed C4 bumps to provide an increased routing density. Benefits include eliminating wet chemical etching that is currently used for the manufacturing of this kind of coreless package.

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Process Flow for First-Level Interconnect Formation in Coreless Package with Mixed/Unmixed  Size Flip Chip Bumps

Disclosed is a method that enables the creation of a coreless package with mixed and/or unmixed C4 bumps to provide an increased routing density. Benefits include eliminating wet chemical etching that is currently used for the manufacturing of this kind of coreless package.

Background

DLL3 coreless packages have superior electrical performance and reduced manufacturing costs. However, one limitation of the current manufacturing process of this type of package is the inability to produce mixed C4 bump sizes for first-level interconnection. Enabling mixed C4 sizes in the coreless technology is essential to meet future generation design rules and performance requirements. The current process necessitates the use of wet chemical etching in conjunction with laserdrilling to do so . Optimizing etching and drilling imposes a limitation of how small the C4 bump can be, and also makes it difficult to form mixed sizes of C4 bumps. Providing the flexibility to produce smaller C4 bumps (for increased routing density) will boost performance opportunities with the DLL3 technology.

In current POR multi-layer core packages, the C4 solder bumps are produced using stencil-based techniques. The SROs are manufactured using photolithography in a layer of solder resist (SR) material. Prior to that step, the SR material is placed on top of the most outer, front side, build up dielectric material. Moving to a coreless substrate, the way solder bumps are manufactured is completely different. There is no solder resist material layer on top of the coreless package. Instead, the solder material is printed in spherical grooves (i.e. dimples) created in a sacrificial copper plate located above the top most build up layer (i.e., the top most layer in this kind of coreless substrate). The sacrificial copper plate is then etched away after the solder material printing step, leaving the required solder bumps on the top of the dielectric layer. The dimple etching and the laser drilling process for the inverted vias in the top most ABF layer are done sequentially after the ABF lamination (see Figure 1a). In POR core packages, mixed C4 bump sizes are created by forming different SRO. Creating different SRO is done by controlling the mask design used in the SR exposure step during the litho process for SR openings. However, it is difficult to create various SRO sizes using the current coreless package manufacturing process flow. The difficulty originates from the need to produce different dimple sizes in the sacrificial copper plate in order to print different solder bump sizes. The process of creating two different groove sizes is extremely difficult because it depends on the etching reaction kinetics, which...