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Stacked Die Interconnect (Die-to-Die Bonding)

IP.com Disclosure Number: IPCOM000103403D
Publication Date: 2005-Mar-17
Document File: 3 page(s) / 46K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a new way of creating a stacked die interconnect. Benefits include eliminating constraints in the die-to-die bonding process.

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Stacked Die Interconnect (Die-to-Die Bonding)

Disclosed is a method for a new way of creating a stacked die interconnect. Benefits include eliminating constraints in the die-to-die bonding process.

Background

Wire bonding is the industry standard that is used to connect a die higher in the stack to a die lower in the stack. However, wire bonding is constrained by pad locations and the wire bond capability, thereby creating constraints on the die-to-die bonding process.

Figure 1 shows an implementation for Logic + DDR DRAM + Flash stacked within one package, using wire bonding as the sole interconnect method. Due to limitations inherent in wire bonding, spacers are used to create physical space for the interconnects.

General Description

The disclosed method uses RDL and bumping technologies to eliminate spacers, and as an added benefit, reduce the package stack-up height. Figure 2 shows an RDL deposited onto die one to add an additional interconnect pad. This pad is tied to other pads on die one (die-to-die interconnects) or to isolated pads which are in turn bonded to the substrate. Figure 3 shows the RDL pattern used on die two to relocate the pad positions if the POR locations are undesirable.

Figure 4 shows the interconnect design on the die one surface. This demonstrates how signals are routed from die two (via the RDL flip chip pads) to either die one (data transfer) or to the substrate (power and grounds).  Path A-B is an electrical signal from die one and die two. Th...