Browse Prior Art Database

Fast Acquisition in a Digital Filter System

IP.com Disclosure Number: IPCOM000103448D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 1 page(s) / 53K

Publishing Venue

IBM

Related People

Coker, JD: AUTHOR [+5]

Abstract

Disclosed addresses the introduction of digital filtering in a digital magnetic recording channel using digital detection as in partial-response maximum-likelihood channels (PRML). This method significantly reduces the startup time of the system.

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This is the abbreviated version, containing approximately 79% of the total text.

Fast Acquisition in a Digital Filter System

      Disclosed addresses the introduction of digital filtering in a
digital magnetic recording channel using digital detection as in
partial-response maximum-likelihood channels (PRML). This method
significantly reduces the startup time of the system.

      When using digital filtering in a magnetic recording channel
using digital detection, the filter is located between the
analog-to-digital (A/D) converter and the rest of the signal
processing hardware which controls the system and performs the
detection.

      There are two control loops, each having two modes of
operation:  acquisition mode and tracking mode.  Acquisition is used
to lock the system clock to the signal and set the signal amplitude
to a determined voltage level in a minimum amount of time.  Once the
loops have converged, the tracking loops take over the job of making
sure the signal remains locked.

      The digital filter introduces more delay in the acquisition
loops.  This has the effect of increasing the time it takes the
system to lock to the signal.  This invention solves this problem by
removing the digital filter function during acquisition, and then
restoring it when the tracking loops are enabled.  To avoid any
problems with startup of the digital filter (i.e., initial
conditions), data is being fed through the filter even though it is
not used.

      The channel block diagram implementing this scheme is shown in
the figu...