Browse Prior Art Database

Fast Sticky for a High Performance IEEE Floating Point Multiplier

IP.com Disclosure Number: IPCOM000103449D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 58K

Publishing Venue

IBM

Related People

Hilker, SA: AUTHOR

Abstract

Disclosed is a method to calculate the sticky (S) bit for rounding for a high performance IEEE Floating Point (FP) double precision multiplier.

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This is the abbreviated version, containing approximately 74% of the total text.

Fast Sticky for a High Performance IEEE Floating Point Multiplier

      Disclosed is a method to calculate the sticky (S) bit for
rounding for a high performance IEEE Floating Point (FP) double
precision multiplier.

      In high performance IEEE FP multipliers, the multiplication of
the fractions can be divided into 4 steps: partial product
generation, partial product reduction to two partial products,
partial product reduction to the exact product, and normalization (1
bit)/rounding to get the final product.

      This method calculates the S bit for rounding and involves
analyzing the least significant 51 bits of the two partial products
that remain after the partial product reduction step that is
accomplished with a Carry Save Adder (CSA) tree or some other type of
adder tree.

      This method calculates the carry out due to the addition of
these two 51 bit (bits 56-106) terms (see Fig. 1).  If the carry out
of these bits is 0, then the S bit is a 0 if, and only
if, the least significant 51 bits of both partial products are all
0s.  This is because any bit (or bits) being a 1 will show up
somewhere in the least significant 51 bit sum if the carry out is a
0.  So, to calculate the S bit when the carry out is a 0, just
OR together the least significant 51 bits of both partial products.

      If the carry out of the least significant 51 bits of the two
partial products is a 1, then the S bit is a 0 if, and only
if, the least significant 51 bits...