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Dynamic Bandwidth DLL for Optimal Lock-In Time

IP.com Disclosure Number: IPCOM000103546D
Original Publication Date: 2005-Apr-16
Included in the Prior Art Database: 2005-Apr-16
Document File: 2 page(s) / 39K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

As the range of operation frequency of DLLs (Dynamic Lock Loops) increases, e.g. in DDR-DRAMs (Double Data Rate-Dynamic Random Access Memories), the difficulty to maintain all aspects of DLL performance over this range also increases. A specific problem is to achieve the standard lock-in time of the DLL at both higher and lower frequencies. The lock-in time of a DLL is related to the loop bandwidth of the DLL. The bandwidth is a function of the clock frequency in the digital filter and the asynchronous delays within the feedback loop. This has the effect that as frequencies increase and the delays remain the same the DLL requires more cycles to complete its lock-in process provided that the filter bandwidth remains the same. Normally the bandwidth of the DLLs is set to achieve lock-in within a certain number of cycles. To accomplish this, the filtering mechanism (normally a low-pass filter) within the DLL controller is set at a high enough roll-off frequency to allow fast locking but slow enough to maintain stability. Figure 1 shows the basic structure of a DLL. The lag time in the feedback loop is dominated by the delay 'dT'. Usually, this lag time causes instability if the filter bandwidth is too high. For example, if the output of the filter changes the delay the filter does not notice this effect until the propagation around the loop is finished. If in the meantime the PD (Phase Detector) sends a signal to the filter telling it to continue to change the delay, having not seen the effects of the previous change, the system will become unstable. If, on the other hand, the filter runs at a sufficiently low frequency (under-sampling) or has a low enough low-pass crossover frequency, the system has time to comprehend each change in delay and will remain stable. This means that the number of cycles needed for stability is directly proportional to freq*dT, where freq has units of cycles/s and dT has units of s. From this one can easily see that for a given 'dT' more cycles are needed at higher frequencies. In the state of the art DLLs, the number of cycles used in the Filter is set to allow for stable operation at the highest expected frequency. This means, however, that the numbers of cycles required for the lock-in will be dominated by the higher frequencies, thus unnecessarily increasing the number of cycles for lock-in at lower frequencies. Therefore it is theoretically possible to decrease the number of lock cycles at lower frequency while maintaining the same filter bandwidth.

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Dynamic Bandwidth DLL for Optimal Lock-In Time

Idea: Aaron Nygren, DE-Munich

As the range of operation frequency of DLLs (Dynamic Lock Loops) increases, e.g. in DDR-DRAMs (Double Data Rate-Dynamic Random Access Memories), the difficulty to maintain all aspects of DLL performance over this range also increases.

A specific problem is to achieve the standard lock-in time of the DLL at both higher and lower frequencies. The lock-in time of a DLL is related to the loop bandwidth of the DLL. The bandwidth is a function of the clock frequency in the digital filter and the asynchronous delays within the feedback loop. This has the effect that as frequencies increase and the delays remain the same the DLL requires more cycles to complete its lock-in process provided that the filter bandwidth remains the same. Normally the bandwidth of the DLLs is set to achieve lock-in within a certain number of cycles. To accomplish this, the filtering mechanism (normally a low-pass filter) within the DLL controller is set at a high enough roll-off frequency to allow fast locking but slow enough to maintain stability. Figure 1 shows the basic structure of a DLL. The lag time in the feedback loop is dominated by the delay 'dT'. Usually, this lag time causes instability if the filter bandwidth is too high. For example, if the output of the filter changes the delay the filter does not notice this effect until the propagation around the loop is finished. If in the meantime the PD (Phase Detector) sends a signal to the filter telling it to continue to change the delay, having not seen the effects of the previous change, the system will become unstable. If, on the other hand, the filter runs at a sufficiently low frequency (under-sampling) or has a low enough low-pass crossover frequency, the system has time to comprehend each change in delay and will remain stable. This means that the number of cycles needed for stability is directly proportional to freq*dT, where freq has units of cycles/s and dT has units of s. From this one can easily see that for a given 'dT' more cycles are needed at higher frequencies. In the state of the art DLLs, the number of cycles used in the Filter is set to allow for stable operation at the highest expected frequency. This means, however, that the numbers of cycles required for the lock-in wi...