Browse Prior Art Database

Microcode Implemented Watchdog Timer

IP.com Disclosure Number: IPCOM000103560D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 1 page(s) / 48K

Publishing Venue

IBM

Related People

East, RE: AUTHOR [+3]

Abstract

Disclosed is a watchdog timer for detecting a so-called hang condition of a single-chip processor while utilizing a minimum of silicon real estate. Such a timer must be able to detect a hung condition of sufficient duration so as to avoid detecting normal system latencies. When a hang is detected, the watchdog timer must produce a failure indication that is unambiguous and identifies hardware failure.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 71% of the total text.

Microcode Implemented Watchdog Timer

       Disclosed is a watchdog timer for detecting a so-called
hang condition of a single-chip processor while utilizing a minimum
of silicon real estate.  Such a timer must be able to detect a hung
condition of sufficient duration so as to avoid detecting normal
system latencies.  When a hang is detected, the watchdog timer must
produce a failure indication that is unambiguous and identifies
hardware failure.

      The method described herein utilizes a hardware latch which
monitors instruction dispatches with microcode which monitors the
dispatch latch.  A single chip RISC processor system contains a
micro-sequencer, 3K words of ROM, and 96 32-bit RAM locations.  Among
its other functions, the microcode updates the real-time clock upper,
a thirty-two bit register that is incremented once each second.
During the update of the real-time clock upper, the microcode
examines the state of the latch, which records instruction
dispatches.  If this latch is not set, indicating that no instruction
dispatch has occurred since the last real-time clock upper update,
one second previous, the microcode enters a checkstop routine.  The
checkstop routine sets an internal latch to indicate the source of
the checkstop, and then issues a command which generates a
system-level checkstop.

      Normally, the real-time clock upper routine detects that
instructions have been dispatched during the past second.
Thereafter, the microcode cle...