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Differential RC Slope Delay Generator

IP.com Disclosure Number: IPCOM000103580D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 142K

Publishing Venue

IBM

Related People

Gillingham, RD: AUTHOR [+3]

Abstract

Performance can be gained in system design if two clock signals can be generated and distributed to each logic chip in the system with each of the two signals being 90 degrees out of phase. The system design requires that the timing skew between edges of the clock signals be minimized. The timing skew must be minimized over process, temperature, and power supply variations. The following circuit provides a method of achieving this which can be implemented entirely on an integrated circuit.

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Differential RC Slope Delay Generator

       Performance can be gained in system design if two clock
signals can be generated and distributed to each logic chip in the
system with each of the two signals being 90 degrees out of phase.
The system design requires that the timing skew between edges of the
clock signals be minimized.  The timing skew must be minimized over
process, temperature, and power supply variations.  The following
circuit provides a method of achieving this which can be implemented
entirely on an integrated circuit.

      The circuit takes a digital input differential reference signal
and converts it from a square wave to a signal that has RC rise and
fall times on the order of one-half of its period.  The capacitors
C0, C1, and resistors R25 and R11 convert the differential signal at
nodes B0-B1 to a differential signal with RC rise and fall times at
nodes NZ1 and NRC in Fig. 2.  This digital input reference signal
with controlled rise/fall times is then fed into two comparators.
The references of the comparators are varied to obtain the
ninety-degree delay.  The Variable Reference takes the Charge Pump
output and varies the two references NVR and NVC in such a manner
that the sum of the magnitude of the two references is equal to the
magnitude of the signal swing at nodes NZ1 and NRC in Fig. 2.  The
NVR and NVC voltages are restricted from being less than 10 percent
or greater than 90 percent of the magnitude of the signal swing at
nodes NZ1 and NRC in the same figure.  The comparators are formed by
the four single-stage differential NPN pairs in the right-hand side
of Fig. 2.

      Differential operation is achieved by connecting the positive
referenced node with a RC rise time in Fig. 2 (node NRC) to a
comparator input with the X percent reference voltage connected to
the opposite polarity comparator input.  At the same time, the
negative referenced node (node NZ1) is connected to a comparator
input with the 100-X percent reference voltage connected to opposite
polarity comparator input.  X refers to the value of the reference
voltage NVR.  100-X refers to the value of the reference voltage NVC.
Th...