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Addressing Mechanism for a Very Long Instruction Word Machine to Allow Recovery from Exceptions

IP.com Disclosure Number: IPCOM000103582D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 86K

Publishing Venue

IBM

Related People

Ebcioglu, K: AUTHOR [+3]

Abstract

Very Long Instruction Word (VLIW) instructions are addressed by the address of the first byte in the instruction. The program counter in such a VLIW processor need not implement the low-order five bits of addressing, because VLIW machines cannot execute part of a VLIW in normal operation. To solve the exception handling problem, the addressing of very long instruction words is extended to include the low-order bits that are not used in addressing very long instruction words. These bits may not be used except by the exception handler; use at any other time is an error. This allows an exception handler written for a non-VLIW machine to be largely reused on a VLIW machine with a similar opcode set.

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This is the abbreviated version, containing approximately 52% of the total text.

Addressing Mechanism for a Very Long Instruction Word Machine to Allow Recovery from Exceptions

       Very Long Instruction Word (VLIW) instructions are
addressed by the address of the first byte in the instruction.  The
program counter in such a VLIW processor need not implement the
low-order five bits of addressing, because VLIW machines cannot
execute part of a VLIW in normal operation.  To solve the exception
handling problem, the addressing of very long instruction words is
extended to include the low-order bits that are not used in
addressing very long instruction words.  These bits may not be used
except by the exception handler; use at any other time is an error.
This allows an exception handler written for a non-VLIW machine to be
largely reused on a VLIW machine with a similar opcode set.

      The program that takes the older, non-VLIW instructions and
creates VLIW programs must order the instructions in the VLIW such
that the instructions that would have been executed first in a
non-VLIW processor are earlier in the VLIW (to the left) than later
instructions or operations.  When an exception occurs, the hardware
must save the results of the operations to the left of the operation
with the exception, save the exception status of the operation with
the exception, and suppress both the results and exception status of
the operations to the right of the operation with the exception.  It
must also load the address of the operation with the exception into
an exception address register.  Note that this address is the address
of the VLIW, with the low-order bits modified to indicate the byte
offset of the operation with the exception.  An exception to saving
results to the left and suppressing results to the right of the
operation with the exception is that the result of all branch
operations must be saved -- either no branch or the branch...