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Browse Prior Art Database

Synchronous External Bus Architecture

IP.com Disclosure Number: IPCOM000103604D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 146K

Publishing Venue

IBM

Related People

Andrews, LP: AUTHOR [+4]

Abstract

Described is a hardware implementation of a synchronous external bus architecture (SEBA) for use with microprocessor-equipped computers to enable signals to be driven over long distances. The design allows a multiplexed bus to be driven from a circuit card with parity checking and provides a burst transfer mode when performing data transfers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Synchronous External Bus Architecture

       Described is a hardware implementation of a synchronous
external bus architecture (SEBA) for use with microprocessor-equipped
computers to enable signals to be driven over long distances.  The
design allows a multiplexed bus to be driven from a circuit card with
parity checking and provides a burst transfer mode when performing
data transfers.

      Typically, for synchronous data transmission, a microprocessor
with a multiplexed bus is used on a circuit card to drive a bus to
other cards across a cable.  In order to drive the bus across the
cable, transceivers are used.  The transceivers generally introduce a
timing delay due to the time required in switching the transceivers
and the propagation delay across the transceivers themselves.  This
delay can cause a problem by skewing critical timing signals for
parity checking.  Other timing problems can occur regardless of the
parity being implemented.

      Parity checking is considered essential in providing data and
address integrity, particularly when signals must be driven over
significant distances.  A microprocessor which utilizes a multiplexed
bus will have specific timing windows for address and data on the
same physical bus.  These timings are considered critical in a
synchronous bus design.

      The concept described herein provides a method to relax the
critical timings by implementing an external synchronous architecture
that allows address and data parity generation and checking to be
performed across the cable.  Figs. 1 and 2 show the bus timings of a
typical microprocessor.  Fig. 1 shows the timing to perform a write
operation and Fig. 2 shows the timing to perform a write operation
plus one wait state.  The CLK-OUT signal is used to synchronize all
events.  The T-states are derived from the CLK-OUT signal by means of
the ALE signal.  The ALE signal indicates a T1 state and all other
states follow in succession with the exception of any wait states
added by the SRDY signal.  The T-states govern the specific timings
indicating address time and data time on the multiplexed bus.

      The process of relaxing the bus architecture timings is to add
one wait state in the data portion of the bus cycle and to expand the
address portion 100 percent from its original bus timings.  This
presents a cycle where the address is 50 percent of t...