Browse Prior Art Database

Automated Microcode Sequence Checks

IP.com Disclosure Number: IPCOM000103605D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 5 page(s) / 209K

Publishing Venue

IBM

Related People

Zimmerman, JP: AUTHOR

Abstract

In a processor that contains a sequencer and microcode, the microcode is intimately coupled with the hardware. There are many restrictions concerning the microcode protocol with the hardware, as well as many code sequences that will cause improper operation of hardware. A method is needed to perform design rules checking on the microcode.

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This is the abbreviated version, containing approximately 32% of the total text.

Automated Microcode Sequence Checks

       In a processor that contains a sequencer and microcode,
the microcode is intimately coupled with the hardware.  There are
many restrictions concerning the microcode protocol with the
hardware, as well as many code sequences that will cause improper
operation of hardware.  A method is needed to perform design rules
checking on the microcode.

      Manual checking is extremely tedious and error-prone.  In
addition, the checking must be performed for all new releases of the
microcode.  For these reasons, the checking must be automated.

      The IBM RISC System/6000*, Model 200/RSC is a related project.
The RSC processor contains a microcoded sequencer to perform a
variety of tasks, including TLB reload, POR, interrupts, and
communicates with the MICRO CHANNEL* interface chip for PIO and DMA
and the Frame Buffer Graphics chip.

      The sequencer consists of 2048 18-bit ROS words, 96 32-bit RAM
locations, and 16 32-bit General-Purpose Registers (GPRs).  The
sequencer can execute at three prioritized processing levels and can
switch processing levels to provide the most efficient service.

      Due to the close interaction of the microcode with the
hardware, a great number of code rules, restrictions, and protocol
definitions arose during the development of the processor.  These
fall into the following general categories:
      - Sequencer Restrictions:

      Due to the design of the sequencer, many code sequence
restrictions apply.  Illegal code sequences have side effects that
cause instructions to be improperly executed, to access wrong RAM
locations, or to improperly switch between processing levels.  In
addition, there are restriction regarding the placement of
instructions relative to its address within a code segment.
      - Performance Rules:

      Microcode rules have been established to allow prioritized
switching and sharing of sequencer resources.
      - Interfaces within the Processor:

      Specific rules have been established when the microcode
utilizes various non-sequencer functions in the processor.  For
example, when the microcode requests a system memory load through the
RSC memory/ cache subsystem, a collection of code rules are required
to insure the memory/cache subsystem is available for the sequencer
request, and that microcode does not use the data until the load has
completed, and that other processing tasks do not interfere with the
sequencer GPRs that are the targets of the load request.
      - Protocol Definitions:

      When the microcode interacts with the MICRO CHANNEL interface
chip or the Frame Buffer Graphics chip, specific protocols have been
established to indicate when data is available, when the devices are
busy, error recovery, etc.

      A factor that complicates the code sequence verification is
that often the code sequences will span conditional branches.  To
completely verify t...