Browse Prior Art Database

(2N+1) State Branch Target Buffer Design

IP.com Disclosure Number: IPCOM000103607D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 3 page(s) / 107K

Publishing Venue

IBM

Related People

Pan, ST: AUTHOR [+2]

Abstract

Branch Target Buffer (BTB) has been widely used to reduce the branch delay by providing the branch target address ahead of decode-time. It is usually worked in conjunction with the instruction fetch unit. A BTB is a small table which is typically organized as a set-associative cache memory. The table keeps the information related to branches. In its simplest form, a BTB retains the information of previously executed taken branches: the branch address tag and the corresponding most recent target address. During the instruction fetch cycle, the table is searched for a match of the branch address tag stored in the table with the tag corresponding to the instruction fetch address. If there is a match (hit), a branch is found and is predicted to be taken.

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(2N+1) State Branch Target Buffer Design

       Branch Target Buffer (BTB) has been widely used to reduce
the branch delay by providing the branch target address ahead of
decode-time. It is usually worked in conjunction with the instruction
fetch unit.  A BTB is a small table which is typically organized as a
set-associative cache memory.  The table keeps the information
related to branches. In its simplest form, a BTB retains the
information of previously executed taken branches: the branch address
tag and the corresponding most recent target address.  During the
instruction fetch cycle, the table is searched for a match of the
branch address tag stored in the table with the tag corresponding to
the instruction fetch address.  If there is a match (hit), a branch
is found and is predicted to be taken.  The corresponding target
address stored in BTB is used to redirect the subsequent instruction
fetching.  If there is no match (miss), the instruction being fetched
is predicted as either a non-branch instruction or a non-taken branch
and instruction fetching continues with the next sequential address.
If an instruction address which misses the table later turns out to
be a taken branch address, a new entry associated with that address
must be inserted into the table.  When a taken branch changes to not
taken,  the corresponding entry in the table is deleted.  Note that
some back-out mechanism must be equipped with the machine to restore
the proper state if the direction or the target of a branch is
wrongly predicted.  The BTB described above is actually implementing
the 1-bit branch prediction scheme as shown in Fig....