Browse Prior Art Database

Mechanism to Allow Soft Stops on a Given Instruction Address

IP.com Disclosure Number: IPCOM000103611D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 1 page(s) / 58K

Publishing Venue

IBM

Related People

Barreh, JI: AUTHOR [+3]

Abstract

Disclosed is a strategy for providing soft-stops on a given instruction address in a super-scalar system. Soft-stops are enabled when a system is in support-processor mode.

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Mechanism to Allow Soft Stops on a Given Instruction Address

       Disclosed is a strategy for providing soft-stops on a
given instruction address in a super-scalar system.  Soft-stops are
enabled when a system is in support-processor mode.

      Support-processor mode allows the processor chips (ICU, FXU and
FPU) to be controlled via logic on the ICU and use of the common
on-chip processor (COP).  In support-processor mode, two basic halt
modes exist: soft and hard.  After a hard stop, the machine cannot be
restarted since the machine's state may be corrupted.  However, after
a soft-stop, the machine may be restarted from the point where the
soft- stop occurred.  Being able to soft-stop on a given instruction
address is invaluable in the debugging of hardware during software
bring-up.

      The ability to soft-stop on a given instruction address is
difficult in a super-scalar design.  This is because multiple
instructions can be dispatched in a single cycle.  The instruction
matching the address of interest must be detected and it must be
interlocked (as well as subsequent instructions) within cycle-timing
constraints.

      An instruction address register (IAR) is generally found in
processor chips.  In a super-scalar design, this register generally
points to the base address of the current dispatch cycle.  For the
purposes of this discussion, one can assume that up to 3 instructions
can be dispatched in a given cycle: I0, I1 and I2 (although...