Browse Prior Art Database

Precise Interrupts with Respect to a Condition Register

IP.com Disclosure Number: IPCOM000103613D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 89K

Publishing Venue

IBM

Related People

Barreh, JI: AUTHOR [+4]

Abstract

Disclosed is a strategy for maintaining the proper state of a condition-register (CR) in order to support precise interrupts.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Precise Interrupts with Respect to a Condition Register

       Disclosed is a strategy for maintaining the proper state
of a condition-register (CR) in order to support precise interrupts.

      Precise interrupts imply that either hardware or software is
able to return the state of the system back to the state that existed
just prior to the instruction that interrupted.  The system can be
considered to be a super-scalar design consisting primarily of three
processors: the icache-unit (ICU), the fixed-point unit (FXU) and the
floating-point unit (FPU).  Hardware is responsible for restoring the
state of the system once an interrupt has occurred.  In a
super-scalar design, multiple instructions are generally issued by
the ICU in a single cycle.  Without a restoration mechanism for the
CR, precise interrupts cannot be supported without severely degrading
the system's performance.  Without such a mechanism, the ICU would be
forced to dispatch one instruction at a time and wait for it to
finish before dispatching the next instruction.

      Instructions that interrupt may be considered to be
interrupt-causing (IC) instructions while instructions that modify
the CR may be called condition-register instructions (CRIs).  CRIs
may be further divided into two classes.  CRIs that must wait for
previous IC instructions to finish before executing may be called
WCRI instructions.  CRIs that do not wait for previous IC
instructions to finish before executing may be called NWCRI.  NWCRIs
are executed solely by the ICU and WCRIs are executed only by the FXU
or FPU.  In order to properly restore the CR upon an interrupt,
snapshots of the CR must be taken whenever NWCRIs are dispatched
after an IC instruction.  Each CR snapshot is placed onto a CR
backup-stack.

      A separate mechanism called the program counter stack (PCS)
exists to decide which, if any, of the CR backup-stack entries is the
proper CR value when an IC instruction interrupts.  A detailed
discussion of this mechanism i...