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Browse Prior Art Database

Microprocessor Mode Select Technique

IP.com Disclosure Number: IPCOM000103614D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Cook, DC: AUTHOR

Abstract

By using the minus byte high enable or not byte high enable (-BHE) pin as a microprocessor mode select, the need for a separate microprocessor mode select pin is eliminated in many chip designs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Microprocessor Mode Select Technique

       By using the minus byte high enable or not byte high
enable (-BHE) pin as a microprocessor mode select, the need for a
separate microprocessor mode select pin is eliminated in many chip
designs.

      On many occasions a chip design must be capable of being used
with different microprocessors for different applications.  In the
case of the Intel 80186 and Intel 80188 families of microprocessors,
the Intel 80186 has a minus or not byte high enable (-BHE) pin and a
16-bit address/data bus while the Intel 80188 has an eight-bit bus.
Logic chip designers usually use a dedicated microprocessor mode
input pin to identify to the logic chip which microprocessor is being
used.

      Shown in Fig. 1 is the 80186 microprocessor connected in a
known manner to a logic chip 10 with the minus or not byte high
enable (-BHE) pin of the 80186 microprocessor and the -BHE pin of the
logic chip 10 interconnected, and with the first bit of the address
A0 of the 80186 microprocessor and of the logic chip also
interconnected.

      The known truth table and functional description valid for the
arrangement shown in Fig. 1 is as follows:
      TRUTH     FUNCTIONAL
      TABLE     DESCRIPTION
 -BHE   A0    ________________
     0    0     two-byte or word wide transfer
     0    1     one-byte transfer on the upper half of the bus
                (D08-D15)
     1    0 ...