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Browse Prior Art Database

Precise Interrupts with Multiple Instruction Streams

IP.com Disclosure Number: IPCOM000103615D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 121K

Publishing Venue

IBM

Related People

Barreh, JI: AUTHOR [+3]

Abstract

Disclosed is a strategy by which interrupt-causing instructions can be tracked across outstanding sequential, conditional and target instruction streams.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Precise Interrupts with Multiple Instruction Streams

       Disclosed is a strategy by which interrupt-causing
instructions can be tracked across outstanding sequential,
conditional and target instruction streams.

      Precise interrupts imply that either hardware or software is
able to return the state of a system back to the state that existed
just prior to the instruction that interrupted.  The system at hand
consists primarily of three processors: an icache unit (ICU), a
fixed-point unit (FXU), and a floating-point unit (FPU).  The ICU
dispatches all FXU and FPU instructions and executes branches.
Branches can be considered to be either conditional or unconditional.
Conditional branches depend on a condition-register (CR) bit in order
to determine whether they are taken or not.  Conditional branches can
be either resolved or unresolved branches depending on whether the CR
is known at the time of the execution of the branch.  In the absence
of unresolved branches, all instructions dispatched by the ICU can be
considered to be part of a sequential stream of instructions.
Unresolved branches, however, can generate two additional streams of
instructions: conditional and target.  Conditional instructions are
those instructions dispatched past an unresolved branch and within
the same sequential stream of instructions as the unresolved branch.
The target of the unresolved branch produces the target stream of
instructions.  Any one of these three streams of instructions may
have interrupt-causing (IC) instructions.  The ICU is capable of
dispatching any one of these three streams once an unresolved branch
has been dispatched.  A mechanism called the program counter stack
(PCS) exists to track the IC instructions.

      The PCS consists of a queue of entries that serve to track
outstanding IC instructions.  Upon an interrupt, the PCS provides the
address of the faulting instruction as well as restoring the value of
architectured registers such as the CR.  The PCS can be thought of as
a circular queue of entries with information on the outstanding IC
instructions within the system.  The IN pointer points to the next
entry to be written within the queue.  The OUT pointer points to the
current entry containing information on the IC instructions currently
being executed by the FXU.  For the purposes of this discussion, the
information contained on each PCS entry includes the addresses of the
outstanding IC instructions and the number of IC instructions
represented by that entry.  PCS entries are written whenever a IC
instruction is dispatched by the ICU.  The IN pointer is incremented
once a PCS entry is written.  PCS entries are removed by
synchronization pulses sent to the ICU by the FXU whenever an IC
instruction is executed.  A PCS entry is removed once the number of
synchronization puls...