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Improvement to the Cycle Steal Process of the 3745 Communication Controller

IP.com Disclosure Number: IPCOM000103624D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 100K

Publishing Venue

IBM

Related People

Galcera, J: AUTHOR [+3]

Abstract

A simple modification to the Cycle Steal (CS) process in a 3745 Communication Controller (CC) is disclosed which significantly reduces the waiting time on most of the CS reads. This dramatically improves the overall performance for some type of protocols in which data are fetched from memory to the input/output buses (process during which cycles are stolen to the CC processor).

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Improvement to the Cycle Steal Process of the 3745 Communication Controller

       A simple modification to the Cycle Steal (CS) process in
a 3745 Communication Controller (CC) is disclosed which significantly
reduces the waiting time on most of the CS reads. This dramatically
improves the overall performance for some type of protocols in which
data are fetched from memory to the input/output buses (process
during which cycles are stolen to the CC processor).

      A communication controller of the IBM 3745 type is equipped
with two IOC buses to get connected to the host and to low-speed
scanners through which teleprocessing lines are managed.  Some
high-speed lines, such as T1s, take advantage of a direct memory
access (DMA) to cope with a much higher data throughput.

      However, for some type of traffic, the bottleneck is not the
performance of the DMA but the IOC Bus throughput.  The gating factor
is then the Main Memory access time.  CS reads do not benefit the
processor cache unless requested data has been previously brought in
by the Network Control Program (NCP).  Then, each time two bytes must
be placed on the IOC bus (a half-word bus) four bytes are fetched in
main store.  Two bytes are discarded.  The remaining two bytes are
sent to the host or to the adapter.

      The discarded data are fetched again later on and so on.  Thus,
two 2-byte transfers on the IOC bus trigger two identical 4-byte
fetches in main memory.  This process is slow not only because of the
double access needed but also because a single fetch does not take
advantage of the paging feature of the dynamic memory.  On top of
this, the main memory might be in use by the DMA.  Because CCU
operations get priority over the DMA ones, a CS may interrupt a DMA
burst in progress, therefore causing contention, and while a CS is in
progress, the processor stops running.  This adds up to the overall
performance impact.

      NCP manages the flow of data and breaks it into buffers at
contiguous locations in main store.  Then CS read process can be
simply improved considerably in the Storage and DMA control card by
prefetching data based on the latest rece...