Browse Prior Art Database

Magnitude Equal Comparator

IP.com Disclosure Number: IPCOM000103626D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 1 page(s) / 46K

Publishing Venue

IBM

Related People

Nguyen, Q: AUTHOR

Abstract

Disclosed is a fast and area-efficient comparator circuit that compares the magnitude and equality of two numbers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 71% of the total text.

Magnitude Equal Comparator

       Disclosed is a fast and area-efficient comparator circuit
that compares the magnitude and equality of two numbers.

      The conventional magnitude comparator is based on the addition
of 2 complement numbers and the check of the overflow for the output.
This requires the complex and slow adder.  Another method uses a
full-blown Karnaugh map expansion for minterms.  This results in a
large layout.  The comparator in this article is simple, fast,
versatile and expandable for long word numbers.

      The circuit for the comparator of this article comprises three
parts: a comparator, a priority decoder and a selector driver.  The
comparator checks, going from MSB to LSB, whether the two aligned
bits are equal.  If they are not equal, then one number must be
larger or smaller than the other.  The corresponding pass devices
will be turned on and determine which bit is larger.  At the same
time, all the pass devices of the lower order bit will be off.  This
is done by the priority decoder with a full look-ahead scheme.

      If the two bits are equal (the output of XOR is 0), then the
checking will interrogate the next lower-order bit.  The same
procedure is followed as in case.  This process continues until the
last bit.

      When the two numbers are equal, the last pass device will be
turned on and the equality output is active (i.e., A=B).  The input
control EQ will allow the comparator to check A > B or A >=...