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Browse Prior Art Database

Simplification to the Updating of the Replacement Pointer in the Cache of the 3745 Communication Controller

IP.com Disclosure Number: IPCOM000103629D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Galcera, J: AUTHOR [+3]

Abstract

Disclosed is the method used to simplify the updating of the Replacement Pointer (RP) in the CACHE of a Communication Controller. In a two-way associative Cache like the one of the communication controller of the IBM 3745 type the replacement pointer is a single bit in the directory. At each Cache reading the directory is updated so that RP points to the line NOT hit. Thus, the next time the same address is read, if none of the two lines contain the address requested (a MISS occurs) the processor knows where the new fetched line is to be placed (thus erasing the Least Recently Used one).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 70% of the total text.

Simplification to the Updating of the Replacement Pointer in the Cache of the 3745 Communication Controller

       Disclosed is the method used to simplify the updating of
the Replacement Pointer (RP) in the CACHE of a Communication
Controller.  In a two-way associative Cache like the one of the
communication controller of the IBM 3745 type the replacement pointer
is a single bit in the directory.  At each Cache reading the
directory is updated so that RP points to the line NOT hit.  Thus,
the next time the same address is read, if none of the two lines
contain the address requested (a MISS occurs) the processor knows
where the new fetched line is to be placed (thus erasing the Least
Recently Used one).

      When a HIT occurs (the requested address is within the CACHE
array) the corresponding data is made available to the processor
within the current cycle either from the A or B side of the CACHE and
there is no need to read RP.

      The only occasion at which RP must be read is when a MISS
happens.  Then, a new line must be fetched in main memory and must
replace another one on the A or B side depending upon the value of
RP.  Line Fetch takes several processor cycles.  It is a slow process
and there is plenty of time to read RP while fetching is in progress.

      Therefore RP must generally be written while the rest of the
directory is read.  This goes on until a MISS occurs at which point
RP must be read to know where to place the line fetch...