Browse Prior Art Database

Coexistent Interrupt Mask Registers

IP.com Disclosure Number: IPCOM000103631D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Clarke, GL: AUTHOR [+6]

Abstract

Disclosed is a circuit providing a pair of eight-bit interrupt mask registers, one of which functions as the master while the other functions as a slave.

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This is the abbreviated version, containing approximately 100% of the total text.

Coexistent Interrupt Mask Registers

       Disclosed is a circuit providing a pair of eight-bit
interrupt mask registers, one of which functions as the master while
the other functions as a slave.

      As shown in the figure, eight data lines 10 are used to set or
reset a master interrupt mask register 12 when data is written to an
address 002CH, as indicated by the output of AND circuit 14, which
provides the clock input to register 12.  Similarly, data lines 10
are used to set or reset a slave interrupt mask register 16 when data
is written to an address 002DH, as indicated by the output of AND
circuit 18.

      Interrupt request signals are provided to this circuit on
sixteen interrupt request lines 20, which, along with mask registers
12 and 16, provide inputs to AND/OR circuits 22 and 24, each of which
is arranged to provide an output signal whenever an interrupt request
signal is present on a line associated with a register bit which has
been set to zero (unmasked).  This association is shown by lines
having the same letter prefix, A through H.

      The output of slave AND/OR circuit 24 provides the IR2Q
interrupt request input to master AND/OR circuit 22, the output of
which provides the interrupt signal DSP INTR.  Thus, if the interrupt
mask bit associated with this input, bit 2 in master mask register
12, is set to one, none of the interrupt request signals provided as
inputs to slave AND/OR circuit 24 will be passed through circuit 22.