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Improved Logic Redundancy Architecture with Performance Enhancements

IP.com Disclosure Number: IPCOM000103639D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 3 page(s) / 135K

Publishing Venue

IBM

Related People

Kemerer, DW: AUTHOR

Abstract

Redundant logic architecture is described that exploits the circuit topology of those logic gates that use emitter followers or source followers as output stage pull-up devices. When used in redundant architecture, these gates require no output multiplexer since their outputs can be connected together if: 1. power is present only on the active gate, and 2. no input signals are connected to the inactive gates. Gated voltage regulators are described which provide the following functions. 1. Selection of active logic gates. 2. Disabling of inactive redundant gates to prevent unwanted power supply current through defective logic. 3. Isolation of the output stage of inactive redundant logic from active logic. 4. Optimization of logic circuit voltage independent of external chip voltage. 5.

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Improved Logic Redundancy Architecture with Performance Enhancements

       Redundant logic architecture is described that exploits
the circuit topology of those logic gates that use emitter followers
or source followers as output stage pull-up devices.  When used in
redundant architecture, these gates require no output multiplexer
since their outputs can be connected together if:
  1.  power is present only on the active gate, and
  2.  no input signals are connected to the inactive gates.
Gated voltage regulators are described which provide the following
functions.
  1.  Selection of active logic gates.
  2.  Disabling of inactive redundant gates to prevent unwanted power
supply current through defective logic.
  3.  Isolation of the output stage of inactive redundant logic from
active logic.
  4.  Optimization of logic circuit voltage independent of external
chip voltage.
  5.  Optimization of logic circuit performance by setting the
circuit voltage to compensate for process parameter variations.
The described combination of elements yields better performance than
other redundant architectures.

      Fig. 1 represents a block diagram of the proposed redundant
logic.  Information supplied to the CHIP PAD OR FUSE CIRCUIT (CPFC)
block determines which one of two rows of logic circuits will be
activated by the REDUNDANCY CONTROLS block (RC).  The RC block
consists of Q1, Q2, Q3 and Q4 in Fig. 2.  A voltage (Vb) determined
by the VOLTAGE BIAS FOR PROCESS COMPENSATION (VBPC) block is fed to
the drains of PFETs Q1 and Q3.  If the CPFC block determines that the
top row of logic circuits is to be active, the gates of Q1 and Q2
are low, Q1 is on, Q2 is off and Vb appears on the ROW SELECT
(RS) rail to turn on gated REGULATOR NPN Q5.  Simultaneously,
inverter I1 turns Q3 off and Q4 on to ground the REDUNDANT ROW SELECT
(RRS) rail and disable gated REGULATOR NPN Q6.  But if the CPFC block
determines that the bottom row of logic circuits is to be active, the
gates of Q3 and Q4 are low, Q3 is on, Q4 is off and Vb
appears on the RRS rail turn on Q6.  The RS rail would then be low
to turn off Q5.

      REGULATOR devices Q5 and Q6 serve several functions.  The RC
block as...