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Browse Prior Art Database

Content Addressable Memory Match Line Power Reduction

IP.com Disclosure Number: IPCOM000103640D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 3 page(s) / 105K

Publishing Venue

IBM

Related People

Gray, KS: AUTHOR

Abstract

A circuit configuration is described that has the ability to selectively enable or disable individual words of a content addressable memory (CAM). Disabled CAM words operate at substantially reduced power compared to enabled words. Chip power dissipation can be reduced by excluding those CAM words that are not needed. Selective disabling and enabling of CAM words allows partially good arrays to be utilized by disabling defective CAM words.

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Content Addressable Memory Match Line Power Reduction

       A circuit configuration is described that has the ability
to selectively enable or disable individual words of a content
addressable memory (CAM).  Disabled CAM words operate at
substantially reduced power compared to enabled words.  Chip power
dissipation can be reduced by excluding those CAM words that are not
needed.  Selective disabling and enabling of CAM words allows
partially good arrays to be utilized by disabling defective CAM
words.

      Fig. 1 shows a CAM word of two bits with its associated match
line.  In a CAM cell of the type shown here, the match line NFET
devices (such as T0 and T1) turn on if the stored cell information
mismatches its own bit line information.  The true (BLT) and
complement (BLC) bit lines are normally low, with data consisting of
short positive pulses as shown in the timing diagrams of Fig. 3.
Longer arrays of CAM words function similarly.

      An empty cell is added at the end of each CAM word in the
manner shown in Fig. 1.  A schematic of the empty cell appears in
Fig. 2 where it is seen that inputs BLTE and BLCE are sampled by the
word line (WL) by means of T4 and T5.  When BLTE and WL are high
simultaneously, a 1 appears at node T and sets the latch composed of
devices T0, T1, T2 and T3.  Similarly, a 1 at node C will reset the
latch.  Two write/ search cycles are shown in Fig. 3 in which the
empty cell is first set, then reset by the data on BLTE and BLCE.
Devices T7 and T9 in Fig. 2 form an inverter to drive the empty cell
true output TOUT, and T6 and T8 drive the complement output CO...