Browse Prior Art Database

On Chip Programmable Timing Mode

IP.com Disclosure Number: IPCOM000103642D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Douse, DE: AUTHOR [+4]

Abstract

By including on-chip circuitry to select appropriate timing via initial program load (IPL) input, chip burn-in testing can be done with extra delay while higher speed operation is used for normal voltage and temperature testing and use. This same technique may be used to adjust a memory chip's array-signal level for obtaining appropriate testing signal margin. Thus, operational circuitry need not have excessive signal margin nor sacrifice speed just to satisfy testing requirements.

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On Chip Programmable Timing Mode

       By including on-chip circuitry to select appropriate
timing via initial program load (IPL) input, chip burn-in testing can
be done with extra delay while higher speed operation is used for
normal voltage and temperature testing and use.  This same technique
may be used to adjust a memory chip's array-signal level for
obtaining appropriate testing signal margin.  Thus, operational
circuitry need not have excessive signal margin nor sacrifice speed
just to satisfy testing requirements.

      Referring to the figure, dynamic random access memory (DRAM) 2
is connected to error correction circuitry (ECC) block 4 by data bus
6.  A signal on strobe line 8 is timed to occur when bus data is
valid, allowing data to be transferred into ECC block 4.  Switch S is
normally closed; therefore, strobe timing is set by delay block D1.

      For burn-in testing, where elevated temperature and voltage is
used, an IPL cycle typically defined by chip column address select
CAS and write W inputs falling before row address select RAS input
with a specific address applied, causes logic in IPL code circuit 10
to open switch S.  Delay D2 is thereby added to delay D1 in strobe
input line 8 to provide appropriate timing for burn-in testing.

      Array-signal level adjustment for signal margin tests may be
made by several means, e.g., 1) word line to sense amplifier set
delay may be adjusted, thereby changing signal development time, or
...