Browse Prior Art Database

MSIS Combining Serialization MP OSC within a Single Control

IP.com Disclosure Number: IPCOM000103653D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 7 page(s) / 383K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+5]

Abstract

The salient features of the CONTROLS that perform and will handle the combination of OSC/MP/SER are described and the means of implementing them jointly are stated in terms of a set of imperatives based on OLD/NEW indicators on FETCHES regarding the detection of the hazards that create roll backs. OSC/MP/SERIALIZATION are all concerned with FETCH and STORE coordination. It is therefore a natural requirement that a single entity, a single set of controls within the processor perform all these functions in combination. The novelty is that the coordination is done at a level above that of the memory hierarchy by a facility that has an effective roll-back mechanism that can address the detection of the hazard.

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This is the abbreviated version, containing approximately 18% of the total text.

MSIS Combining Serialization MP OSC within a Single Control

       The salient features of the CONTROLS that perform and
will handle the combination of OSC/MP/SER are described and the means
of implementing them jointly are stated in terms of a set of
imperatives based on OLD/NEW indicators on FETCHES regarding the
detection of the hazards that create roll backs.
OSC/MP/SERIALIZATION are all concerned with FETCH and STORE
coordination.  It is therefore a natural requirement that a single
entity, a single set of controls within the processor perform all
these functions in combination.  The novelty is that the coordination
is done at a level above that of the memory hierarchy by a facility
that has an effective roll-back mechanism that can address the
detection of the hazard.  In the context of MSIS (Multisequencing a
Single Instruction Stream) the Z-CODE can at initiation signal that
it contains SERIALIZERS, and the coordinated action that is derived
from the single controls can be sensitive to the anticipation of a
SERIALIZATION requirement.

      MSIS is a uniprocessor organization in which a set of
processing elements (PEs) working in concert execute Segments of the
instruction stream.  The Segments are either P-Segments, normal
uniprocessor instruction stream portions, that are processed in the
E-MODE of MSIS and produce Z-Segments, or the Z-Segments that are
processed in Z-MODE by MSIS.  The main difference between E-MODE and
Z-MODE is that during E-MODE each PE sees all instructions in the
Segment and executes the ones that are assigned to it, but during
Z-MODE, a PE only sees the instructions assigned to it.

      As all PEs see all instructions in E-MODE, each PE can create
the Z-CODE it will require to re-execute the Segment as a Z-Segment,
the Z-CODE being stored in the Z-CACHE, and associated with
instructions in the Z-CODE are S-LISTS and D-LISTS as appropriate.
An S-LIST instructs the PE, in the Z-MODE, that one or more of the
source registers in an instruction assigned to it is set by another
instruction that is executed on another PE, an S-LIST is a receiving
obligation.  The D-LIST instructs the PE in the Z-MODE as to the
names of PEs that require the values of the register(s) that are
being set by an instruction that is assigned to it.  A D-LIST entry
is a sending obligation.

      The set of FETCHES and STORES that are within a repository
associated with each processor, said repositories periodically pruned
as the level of conditionality (LC) progresses, represent the extent
that the processors individually and collectively differ from the
state of the system as manifest in the memory hierarchy.  The system
state regarding registers is handled via a separate mechanism.  The
roll-back mechanism cures both Branch Wrong Guess (BWG) and hazards
of the type considered: OSC MP SER, at a level that is above the
memory hierarchy and thus does not depend on a particular memory
hierarchy to support it.

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