Browse Prior Art Database

Multi-staged Memory Test

IP.com Disclosure Number: IPCOM000103654D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 1 page(s) / 38K

Publishing Venue

IBM

Related People

Barrera, DD: AUTHOR [+9]

Abstract

Disclosed is the invented multi-staged memory test which provides flexibility and performance improvement.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 98% of the total text.

Multi-staged Memory Test

       Disclosed is the invented multi-staged memory test which
provides flexibility and performance improvement.

      State of the art memory testing is single-staged.  It is
single-staged because non-volatile RAM is used concurrently during
the memory test and because the memory test is executed out of ROM
instead of the system memory (RAM).  Obviously, it is not efficient
and lacks flexibility.

      The disclosed invention uses the concept of multiple stage
testing to enhance the flexibility and performance.  At any given
stage, only the absolute minimum amount of memory gets tested.  For
example, in the IBM RISC System/6000* model 220 implementation, the
first stage involves testing only 96 bytes of memory.  This allows
the establishment of a memory configuration table, etc.  The second
stage involves testing 30K bytes of memory.  This allows part of the
memory checking code to be moved from ROM (where IPL code resides) to
system memory.  After the code gets moved to the system memory, the
memory test will speed up significantly due to relative fast
instruction execution out of system memory (compared to out of ROM).
The subsequent stages involve the same data test but different
objectives, such as finding the memory for the IPL control block,
etc.

      As mentioned above, a multi-staged memory test offers many more
benefits than the single-staged memory test, both in terms of memory
utilization and efficiency.
* ...