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Combined Translation Lookaside Buffer for Page Frame Table and Translation Control Word Entries

IP.com Disclosure Number: IPCOM000103656D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 3 page(s) / 106K

Publishing Venue

IBM

Related People

East, RE: AUTHOR [+3]

Abstract

Two different address translation mechanisms, the Translation Control Word (TCW) and the Page Frame Table (PFT), share a common cache.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Combined Translation Lookaside Buffer for Page Frame Table and Translation Control Word Entries

       Two different address translation mechanisms, the
Translation Control Word (TCW) and the Page Frame Table (PFT), share
a common cache.

      This invention is used on the Single-Chip processor.  A
translation lookaside buffer (TLB) had been designed to support the
normal virtual to real address translation mechanism used on the IBM
RISC System/6000* family of processors.  This method of translation
is called the page frame table or PFT type translation.  It was also
necessary to include a mechanism to support the translation of
addresses to system memory which are the result of DMA operations.
This type of translation where I/O operations are mapped to system
memory is called translation control word or TCW translation.  The
optimum solution would be to combine the two functions into a single
cache.

      The following diagrams show the way the PFT and TCW entries are
stored in the combined TLB.
TLB ENTRIES (PFT ENTRY)

                            (Image Omitted)

0..3       VPI = Low 4 bits of the VPI.
4           V  = Valid bit this is set by the sequencer and can be
turned off with a TLBI instruction.
0.5..19    RPN = Real Page Number for the associated Virtual Page
Index.
20          C  = Change bit indicates that the page has been
modified.
21..22      PP = Page Protection bits indicate the type of access
allowed.
23           T  = Type of entry where 0 = I/O and 1 = non I/O.
24..31      VPI = High 8 bits of the VPI.
33..56      SID = Segment ID for this entry.
TLB ENTRIES (TCW ENTRY)

                            (Image Omitted)

0..3         X  =  Don't cares
4            V  = Set to 0 for IO indicates invalid pft entry.
5..19       RPN = The Real Page Number
20..21       X  = Don't Care
22           I  = Invalid bit 0 = entry valid 1 = entry invalid.
23           T  = Type of entry 0 = I/O and 1 = non I/O.
24           X  = Don't Care
25..27      KEY = Page Protection key into authority field.
29           C  =...