Browse Prior Art Database

Semiconductor on Insulator Process by Selective Removal of Epitaxial Layers

IP.com Disclosure Number: IPCOM000103658D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 3 page(s) / 97K

Publishing Venue

IBM

Related People

Sun, Y: AUTHOR

Abstract

Disclosed is a new method to form VLSI device quality Semiconductor on Insulator (SOI) islands. The method involves the elective removal of a heavily doped epitaxy layer and subsequent insulator formation around and under the lightly doped, epitaxially grown single-crystalline semiconductor islands. This technique offers a better control of the quality and thickness of the SOI layer as compared to other methods, such as oxygen implantation or bond and etchback.

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Semiconductor on Insulator Process by Selective Removal of Epitaxial Layers

       Disclosed is a new method to form VLSI device quality
Semiconductor on Insulator (SOI) islands.  The method involves the
elective removal of a heavily doped epitaxy layer and subsequent
insulator formation around and under the lightly doped, epitaxially
grown single-crystalline semiconductor islands.  This technique
offers a better control of the quality and thickness of the SOI layer
as compared to other methods, such as oxygen implantation or bond and
etchback.

      One preferred embodiment (fabrication sequence) for silicon SOI
is illustrated in Fig. 1.
1.  The starting single crystalline substrate has a lightly doped (or
intrinsic) surface layer. A heavily doped (p+) layer is grown by
epitaxy such as ultra high vacuum low temperature CVD (UHV/CVD).
High quality p++-Si layer doped with boron to more than 1020 cm-3 can
be routinely achieved by adding a fraction of germanium for strain
compensation.  Grooves (Fig. 1a) are then etched through the p++
layer and stopped at the intrinsic layer by conventional resist
masking and reactive ion etch (RIE) schemes.
2.  Intrinsic silicon is grown in the groove (Fig. 1b) by
conventional selective epitaxy, with or without an oxide liner on the
sidewall of the groove.  This i-layer in the groove will serve as the
etch stop between adjacent p++ islands.  It will also support the SOI
layer when the p++ layer underneath is etched away.  It may be
replaced by oxide or any other good insulator which is, not o...