Browse Prior Art Database

Instruction Set for RCS Microsequencer

IP.com Disclosure Number: IPCOM000103662D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 3 page(s) / 129K

Publishing Venue

IBM

Related People

Elliott, TA: AUTHOR [+4]

Abstract

On a processor that is partially controlled by a microsequencer, the selection of the sequencer instruction set is critical to the overall function and performance of the processor. This article describes the selection of the instruction set of the RSC microsequencer and how this selection balanced efficiency, performance, and interface requirements.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Instruction Set for RCS Microsequencer

       On a processor that is partially controlled by a
microsequencer, the selection of the sequencer instruction set is
critical to the overall function and performance of the processor.
This article describes the selection of the instruction set of the
RSC microsequencer and how this selection balanced efficiency,
performance, and interface requirements.

      A related project is the IBM RISC System/6000*, MODEL 200/RSC.
The RSC single-chip IBM RISC System/6000 processor contains a
micro-sequencer, 3K words of ROM, and 96 32-bit RAM locations.  The
sequencer performs the following functions: the RSC single chip IBM
RISC System/6000 processor contains a microsequencer, 3K words of
ROM, and 96 32-bit RAM locations.  The sequencer performs the
following functions:
      - TLB reload for virtual address translations
      - power on reset sequencing of the processor
      - IOCC functions, including control for DMA transfers, control
for PIOs, and maintenance of the TCW tables
      - real-time clock and decrementer function
      - external interrupt processing
      - maintenance of various architected power registers, including
the msr, srr0, srr1, and many special-purpose registers.
      - error recovery for I/O errors, machine checks, check stops,
and single and double bit ECC errors.

      This list demonstrates the wide range of tasks the sequencer
performs.  To accomplish this, the instruction set associated with
the sequencer must efficiently be able to interface with an external
I/O chip, the RSC cache controller, the fixed point execution unit,
and a variety of local registers and control signals.  In addition,
the instruction set must allow for standard arithmetic, logical, test
and branch operations so that efficient microcoding of these
functions can occur.

      The instruction set must also remain small and stay within a
predefined word size due to space constraints of the RSC processor.

      The following list categorizes the instruction set used by the
RSC sequencer.
   - Immediate instructions.  These allow 16-bit constants to be
created from an immediate field contained in the instruction.
   - Branches
   - Conditional branch based on state of register or RAM bit.
Allows branching within a 64-word page.
       - Unconditional branch, allowing a branch to anywhere within
the 3K word space.
       - Branch and link to subroutine.  Allows a branch with link to
anywhere within the 3K word space.
       - Branch and link halt.  This completes a routine and allows
the sequencer to poll for service requests.
       - Branch and link with Poll Service.  This allows a microcode
routine to poll for higher priority tasks awaiting service.  It also
allows the sequencer to wait at busy conditions.
     ...