Browse Prior Art Database

Asynchronous Queued I/O Processor Architecture

IP.com Disclosure Number: IPCOM000103668D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18

Publishing Venue

IBM

Related People

Mott, JM: AUTHOR [+2]

Abstract

This article describes an I/O processor architecture, named AQ/IOP, which could be used in the implementation of high-speed communication adapter design such as HIPPI or FCS. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 14% of the total text.

Asynchronous Queued I/O Processor Architecture

       This article describes an I/O processor architecture,
named AQ/IOP, which could be used in the implementation of high-speed
communication adapter design such as HIPPI or FCS.

                            (Image Omitted)

      The AQ/IOP architecture supports:

      (1) Synchronous I/O: The I/O processor is required to generate
an external interrupt to the host processor when the request has been
processed and completion code status posted.

      (2) Asynchronous I/O: The I/O processor is not required to
notify the processor that the request has been processed.  At the end
of the I/O transaction, the I/O processor will return a completion
code status and proceed with the next I/O request.

      (3) Queued I/O: The I/O requests shall be structured in a list.
The host processor only needs to interrupt the I/O processor with the
address and length of the list to signal that there are new I/O queue
element(s) which need to be looked at.  The I/O processor is
responsible for DMA the I/O control block(s) and process the I/O
requests without interrupting the host processor unless requested by
the I/O transaction.  The I/O control block(s), associated data
structures, and user data area are pinned for the duration of the
transaction.  The user process can add requests to the I/O queue and
interrupt the I/O processor to signal updates to the queue.  I/O
requests which belong to the same conversation are required to be
processed in the order they are issued.  Out of order processing is
acceptable for I/O requests which are from different conversations.

      (4) Unsolicited I/O: The data is transferred to a designated
temporary storage area which is set up during initialization.  The
I/O processor generates external interrupt for each unsolicited I/O
transaction.  Lack of temporary storage (either due to processor
falls behind processing external interrupt or not allocated) will
result in data lost.

      (5) Circular status queue: To signal the host in the case of
synchronous I/O requests or unsolicited I/O requests, the I/O
processor is required to manage a circular queue of I/O status.  When
an I/O request comes in which requires the host system attention, the
I/O processor will store a I/O status element into the circular queue
and then generates an external interrupt.  The I/O status element is
in the same format as the I/O Queue element control block with all
the fields filled in with information that the host system requires
for processing the I/O request.  The circular status queue base and
bound addresses are defined during initialization.  There are 2 queue
pointers, one controlled by the host system and one controlled by the
I/O processor, which are used for the management of the circular
status queue.

      (6) Frame buffer I/O: Data transfer from host memory or I/O
channel to frame buffer is supported.  In ad...