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Browse Prior Art Database

Offset Equalizing Scheme for 2/3 VDD Sensing

IP.com Disclosure Number: IPCOM000103672D
Original Publication Date: 1993-Jan-01
Included in the Prior Art Database: 2005-Mar-18
Document File: 4 page(s) / 136K

Publishing Venue

IBM

Related People

Yoshikawa, T: AUTHOR

Abstract

Disclosed is a bitline equalizing scheme in order to make a higher bitline precharge voltage (2/3 VDD bitline precharge voltage) which is quite effective to perform faster sensing and obtain larger signal margin compared to ordinary 1/2 VDD bitline precharge volatge in CMOS Dynamic Random Access Memory (DRAM).

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This is the abbreviated version, containing approximately 52% of the total text.

Offset Equalizing Scheme for 2/3 VDD Sensing

       Disclosed is a bitline equalizing scheme in order to make
a higher bitline precharge voltage (2/3 VDD bitline precharge
voltage) which is quite effective to perform faster sensing and
obtain larger signal margin compared to ordinary 1/2 VDD bitline
precharge volatge in CMOS Dynamic Random Access Memory (DRAM).

      A sense amplifier which is used in ordinary CMOS DRAM is shown
in Fig. 1.  In DRAM standby phase, BL, /BL, PSB and PSDP are floated
and on the same voltage value.  When DRAM is activated, the data
which corresponds to selected Row Address appears in BL as
appropriate one hundred and fifty millivolt voltage differences to
/BL.  Then PSB goes to ground value gradually as primary sensing and
pulls down one of two bitlines to ground.  After a certain time, PSDP
goes to VDD value and pulls up another bitline to VDD.  In primary
sensing, bitline precharge voltage is quite equal to drain and gate
voltage of cross- coupled NMOS transistors (TN1 and TN2).  Hence,
higher bitline precharge voltage contributes to faster sensing
because TN1 or TN2 obtains larger Vgs and Vds.  On the other hand, it
is harder for PMOS cell to retain physical 0 value than to retain
physical 1 value because of the leakage between N-Well and storage
node.  When physical 0 value is stored, bitline is equal to source
node of selected PMOS cell (TPC1).  Hence, higher bitline precharge
is effective to get larger signals from cells because TPC1 obtains
larger Vgs and Vds.  Because of above mentioned things, higher
bitline precharge voltage is effective to perform faster sensing and
obtain larger signals.

      The conventional way to set bitline to higher precharge voltage
is as following: At first, BL and /BL are shorted by forcing PEQ low
and set to 1/2 VDD voltage by static charge sharing of them.  Then
TPE1 is turned on by /PULSE and pull BL and /BL up to appropriate
voltage through VEQ node.  Fig. 2 shows the bitline voltage waveforms
in conventional DRAMs.  This way has two problems.  One is noise in
VDD line which is caused by high peak current in pulling bitlines up
because the load of bitlines and VEQ node is very heavy.  Another is
long b...